Re: [oopic] Re: Angle of attack VII - any help appreciated

ah hah - yep I think I get what you mean ... I'll search for a proper
4-bit counter a bit harder as locally there is only that BCD one I've
found so far ... Unless as I understand it the second chip I linked
(the Asynchronous Clear SN54HC193/SN74HC193) is fine ? So we wouldn't
use CLR in the scheme you outlined huh - as in LOAD is 'synchronous'
or doesn't cause timing issues ?

erm, could you just ground LOAD and have A,B,C,D all grounded as well
to achieve the same as CLR ?

Just a quick question to help lubricate my understanding !

thanks ;)
Nick

On 7/21/07, rtstofer <rstofer@pacbell.net> wrote:
> --- In oopic@yahoogroups.com, "Nick Mulder" <nick.mulder@...> wrote:
> >
> > Okidoki,
> >
> > Locally (and cheaply) I can get the 74HC160 Synchronous Decimal
> > Up/Down Counter - http://www.jaycar.co.nz/products_uploaded/ZC4855.pdf
> > - It seems to be the same chip aside from the fact it is BCD and not
> > the full 2^4 bits
>
> Better check page 2 of 12 where it states that the Clear input is
> asynchronous. However, the Load' input is synchronous. All you have
> to do is load a value of 0.
>
> >
> > Now if I'm understanding correctly it should work fine but I need a
> > different setup of logic doohickeys for the reset and 13th(12th)
> > outputs ?
> >
> > Either that or maybe:
> > http://www.jaycar.co.nz/products_uploaded/ZC4864.pdf - which is a
> > different beast but in the same ballpark ?
>
> Again, this chip also has asynchronous clear. Unfortunately, it also
> has asynchronous load.
>
>
>
> Since you only want an output every 12 or 13 pulses, you can use a
> single counter (74HC163) and a D flop such as the 74HC74. What we can
> do is count 1..12 (12 count) or 0..12 (13 count). We generate the
> LOAD' (PE') signal by NANDing Q3 and Q2 (12). We ground the D3, D2 &
> D1 inputs and connect the D0 input to the Q output of a D flop. The D
> input of the D flop is the Q' output of the flop and the clock is the
> LOAD' signal.
>
> Assume the D flop is reset. The Q output is 0 so when the counter
> reaches 12, the counter will load with 0 and the D flop will toggle.
> When the counter reaches 12 (13 clocks later) the Q output will be one
> and the counter will load with 1. The Q output of the D flop will
> toggle back to 0 so that 12 clocks (counts 1..12) later the counter
> will be loaded with 0 again.
>
> Richard
>
>
>
>
>
> Yahoo! Groups Links
>
>
>
>

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