--- In oopic@yahoogroups.
>
> If you use a counter with a synchronous reset (reset occurs at clock
> edge) then things get a lot easier.
>
> Consider 2 74LS163 4 bit synchronous counters. Clock both together.
> Connect the Ripple Carry Output of the low order counter to the Enable
> T input of the high order counter. Ground the Enable T input of the
> low order counter. Ground all the Data inputs, the Enable P inputs
> and the Load inputs.
>
> Now, decode Q4 (the low order bit of the high order counter) AND Q3
> (the high order bit of the low order counter) as a count of 24 and run
> that to the Reset input. The counters will now count 0..24.
>
> Since you have decoded the 25th count (count = 24) all you have to do
> is decode the 13th count (0..12) so: AND together Q3 and Q2 (the high
> two bits of the low order counter).
OOPS! The count of 24 will last for 1 clock because the counter
resets but the count of 12 will last a lot longer - 4 clocks.
The proper decode for count = 12 (13th pulse) is Q3 AND Q2 AND (Q1 NOR
Q0).
>
> Richard
>
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