--- In oopic@yahoogroups.
>
> Just reading up on the part ...
>
> Still way behind you in terms of knowing this stuff - really need to
> read up on the basics - logic gates, JK flip flops and the like ...
>
> I'll get down to nutting it out shortly - suspect I'll need to turn
> down the music and draw me a picture with bunnywabbits, truth tables
> etc...
>
> Damn spec sheets are written *too efficiently* for me - nothing but
> the required info huh, no '74LS163 for dummies' or 'rtstofer for
> dummies' for that matter ;)
>
> cheers for the update, imagine I would have been quite confused
without it !
> Nick
The reason for wanting synchronous reset is that there won't be a
glitch at the end of the count. If you try an asynchronous reset,
there will be an instant where the count will be 25 just before it
clears to 0. Maybe that matters, maybe it doesn't. Maybe you get a
complete reset, maybe you don't.
Back to that 74LS163: from the timing diagram, LOAD needs to be a '1'
for normal counting as does ENABLE P and ENABLE T. For the low order
counter pull them all high. On the high order counter, connect ENABLE
P and ENABLE T to the Ripple Carry Out of the low order counter. The
LOAD signal of the high order counter needs to be '1'.
There are some good examples here:
http://people.
I haven't thought about discrete counters in a very long time. It is
so much easier to build a synchronous counter in a CPLD or FPGA. A
very few lines of code and its done! Let the synthesis tool do all
the grunt work! When you have 1M gates in a single package almost
anything is possible.
Richard
Change settings via the Web (Yahoo! ID required)
Change settings via email: Switch delivery to Daily Digest | Switch format to Traditional
Visit Your Group | Yahoo! Groups Terms of Use | Unsubscribe
__,_._,___
No comments:
Post a Comment